Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS

Flip-flops (FFs) are key building blocks in the design of high-speed energyefficient microprocessors, as their data-to-output delay (D-Q) and power dissipation strongly affect the processor’s clock period and overall power [1]. From previous analyses [2], the Transmission-Gate Pulsed Latch (TGPL) [3] proved to be the most energy-efficient FF in a large portion of the design space, ranging from high speed (minimizing EDj products with j>1) to minimum ED product designs [2], while simple Master-Slave FFs (TGFF [1] and ACFF [4]) are the most energy efficient. TGPL also has the lowest D-Q delay along with STFF [5]. However, the latter has considerably worse energy efficiency [2], hence, the TGPL is the best reference for a comparison. In this work, two new FFs are introduced, the Conditional Push-Pull Pulsed Latch (CP3L), and a version with a Shareable (CSP3L) Pulse Generator (PG). The adoption of a fast push-pull second stage, which requires a conditional PG, enables 50-to-100% delay improvements compared to TGPL, and absolute D-Q up to 0.7FO4. CP3L and CSP3L also exhibit superior energy efficiency to TGPL in terms of minimum ED3 and ED products. A test chip is fabricated in 65nm CMOS technology (VDD=1V) to measure delay and energy consumption of CP3L, CSP3L and TGPL in minimum ED and ED3 sizings. Different loadings are used in the minimum ED (16×) and the minimum ED3 (64×) cases.